Blitz India Business
NEW DELHI: India’s semiconductor programme has sanctioned more capital than most of its manufacturing missions combined. The useful metric this month is not the money approved — it is how many of the twelve plants are actually shipping.
Total approved investment under the India Semiconductor Mission stands at about ₹1,65,685 crore across six states, spread over twelve commercial facilities. Three of those twelve are now operational. That ratio — one in four — is the honest measure of where the programme has reached, and it is a good deal more informative than the sanction figure, which has been quoted unchanged for months.
What is running is packaging and testing rather than fabrication. Kaynes Semicon’s assembly and test facility at Sanand was inaugurated on 31 March 2026. The Tata–PSMC 300-millimetre wafer fabrication line at Dholera is targeting first silicon by December 2026, and Tata Electronics signed an agreement with the Dutch equipment maker ASML on 16 May 2026 for a front-end fabrication plant in Gujarat. The Union Electronics Minister’s own timeline has four plants operational by the end of 2026, two more in 2027, and India’s first full fabrication unit at Dholera by 2028.
Packaging first, fabrication next: the three operational units do assembly and test. The first 300 mm wafer line at Dholera is targeting first silicon by December 2026.
Three of twelve, and all three in packaging. That is the correct order — every semiconductor economy in Asia built assembly and test before it built a fab.
At a Glance
• Approved investment: about ₹1,65,685 crore under the India Semiconductor Mission
• Spread: six states, twelve commercial facilities
• Operational now: three of twelve
• Kaynes Semicon OSAT, Sanand: inaugurated 31 March 2026
• Tata–PSMC, Dholera: 300 mm line, first silicon targeted December 2026
• Tata Electronics and ASML: agreement signed 16 May 2026, front-end fab in Gujarat
• Stated timeline: four plants by end-2026, two more in 2027, full fab at Dholera by 2028
• Current output type: assembly, test and packaging — not wafer fabrication
The sequencing is worth defending, because it is regularly misread as a shortfall. Assembly, test, marking and packaging is where every Asian semiconductor economy began — Malaysia, Taiwan, Korea and China each built back-end capability, workforce and supply-chain discipline before committing to front-end fabrication. A packaging plant employs a large trained workforce, establishes chemical and gas supply chains, and creates the customer relationships a fab later needs. Skipping it produces expensive fabs with nothing around them.
The number the sector should be watching between now and December is therefore first silicon at Dholera, not the next sanction announcement. A 300-millimetre line reaching first wafer on schedule would validate a construction and equipment-installation timeline that very few countries have met on a first attempt, and it would convert a sanctioned figure into an operating asset. The realistic risk is not capital — that is committed — but specialist installation and process-engineering talent, which is scarce worldwide and being competed for by every new fab under construction. The constructive path is already visible in the ASML tie-up and in the training programmes attached to the operating packaging units: build the people alongside the buildings. Three of twelve is where India is. The ratio is what to check next quarter.